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HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
DESCRIPTION
HB7122B is a highly integrated single chip CMOS B/W image sensor using Hyundai 0.5um CMOS process developed for image application to realize high efficiency photo sensor. The sensor has 414X314 pixels total, and 400X300 pixels effective. Each pixel is high photo sensitive, small size active pixel element that converts photons to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert (DAC) and 414 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for independent gain control. Hyundai proprietary on-chip Correlated Double Sampling (CDS) circuit can reduce Fixed Pattern Noise (FPN) dramatically. The whole 8 bit digital B/W raw data is directly available on the package pins and just a few control signals are needed for whole chip control, so it is very ease to configure a system using the sensor.
FEATURES
l l l l l l l l 400 x 300 pixels resolution 8um x 8um square pixel High efficiency photo sensors Integrated 8-bit ADC for direct digital output Low power 3.3V operation (5V tolerant I/O) Integrated pan control and window sizing Clock speed up to 15MHz Programmable frame rate and synchronous format l l l l l l l Full function control through standard I2C bus Built-in Automatic Gain Control (AGC) 48 pin CLCC Anti-blooming circuit Flexible exposure time control Integrated on-chip timing and drive control 1/4" optical format
TECHNICAL SPECIFICATION
Pixel resolution Pixel size Fill factor Format Sensitivity Supply voltage for analog Supply voltage for digital Supply voltage for 5V tolerant input Power Consumption Operating temperature Technology 402x302 30% CIF 8.0V/luxsec 3.3V 3.3V 5.0V
FUNCTIONAL BLOCK DIAGRAM
Decoder/Pixel Driver
8x8um2
Control Register & Logic
I2C
Pixel Array
ADC Block Line Buffer
TBD@15MHz
0~40 Centigrade 0.5um 3metal CMOS
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -11999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings l l
l l
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
Supply voltage(Analog, Digital) Voltage on any input pins Operating Temperature(Centigrade) Storage Temperature(Centigrade)
: : : :
-0.4 V -0.4 V 0 -30
~ ~ ~ ~
3.8 V VDD + 0.5 V 40 80
Note : Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions Symbol Vdd Vih Vil Voh Vol Ta Parameter Internal operation supply voltage Input voltage logic "1" Input voltage logic "0" Output voltage logic "1" Output voltage logic "0" Ambient operating temperature Units Volt Volt Volt Volt Volt Celsius Min. 3.0 2.0 0 2.15 0.4 0 Max. 3.6 5 0.8 3.6 0.4 40 6.5 6.5 60 60 Load[pF] Notes
AC Operating Conditions Symbol MCLK SCK
2
Parameter Main clock frequency I C clock frequency
Max Operation Frequency 20 400
Units MHz KHz
Notes 1 2
1. MCLK can be divided according to Clock Divide Register for internal clock.
2. SCK is driven by host processor. For the detail serial bus timing, refer to I2C Spec.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -21999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
ELECTRO-OPTICAL CHARACTERISTICS
color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mmt) is used.
Parameter
Sensitivity Dark Signal Output Saturation Signal Dynamic Range Output Signal Shading Dark Signal Shading Frame Rate Note:
Units
mV / luxsec mV/sec mV dB % mV/sec fps
Min.
Typical
8000
Max.
50
Note
1) 2) 3) 4) 5) 6) 7)
1200 48 8 13 10 60
1) Measured at 8lux illumination for exposure time 10 ms. 2) Measured at zero illumination for exposure time 50 ms. (Ttemp = 40 Centigrade) 3) Measured at Vdd =3.3V and 100lux illumination for exposure time 50msec. 4) 48dB is limited by 8-bit ADC. 5) Variance of average value of 4x4 pixels response of each block over all equal blacks at 50% saturation level illumination for exposure time 10msec. 6) Range between Vmax and Vmin at zero illumination for exposure time 50msec, where Vmax and Vmin are the maximum and minimum values of each block' s response, respectively. 7) Measured at MCLK 15MHz. Integration time must be set in order for effective window height not to exceed window height. It' s because effective window height is directly proportional to integration time.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -31999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
INPUT / OUTPUT AC CHARACTERISTICS
l l l
All output timing delays are measured with output load 60[pF]. Output delay include the internal clock path delay 6[ns] and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, output signals may be latched in the negative edge of MCLK for the stable data transfer between the image sensor and a host for less than 15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1
MCLK HSYNC/VSYNC T2
T1
T1 : MCLK rising to HSYNC/VSYNC valid maximum time : 18ns [output load: 60pF] T2 : HSYNC/VSYNC valid time : minimum 1clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3 MCLK DATA[7:0] valid data
T3
T3 : MCLK rising to DATA valid maximum time : 18ns [output load: 60pF] Note) HSYNC signal is high when valid data is on the DATA bus.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -41999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
T4
T5
MCLK
T6 ENB
T
T4 : ENB Setup Time : 5[ns] T5 : ENB Hold Time : 5[ns] T6 : ENB valid Time : minimum 2 clock
RESET Timing Must in Valid (active low) state at least 8 MCLK periods
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -51999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division INPUT
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
/ OUTPUT AC CHARACTERISTICS CONTINUE
I2C Bus (Programming Serial Bus) Timing
stop
start
start
stop
SDA
tr tbuf tf tlow thd;sta
SCK
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
I2C Bus Interface Timing Parameter SCK clock frequency Time that I2C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of each bus lines(SDA,SCK) Symbol fsck tbuf thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Cb 1.2 Min. 0 1.2 1.0 1.2 1.0 1.2 1.3 250 250 300 Max. 400 Unit KHz us us us us us us ns ns ns us pf
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -61999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division PIN CONFIGURATION (48 pin CLCC)
PIN NO. 1 2 3 4 5 6 7 8 17 18 21 22 23 24 25 Pin9~16, Pin19~20, Pin33~41 : No Connection NAME SCK DGND ENB DGND MCLK VDD5 AVDD AGND AGND AVDD DGND DATA7 DATA6 DATA5 DATA4 PIN NO. 26 27 28 29 30 31 32 42 43 44 45 46 47 48 NAME DGND DATA3 DATA2 DATA1 DATA0 DVDD DGND DVDD RESET VSYNC HSYNC DGND SDA DGND
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -71999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division PIN DESCRIPTIONS (48 Pin CLCC) PIN
1 2 3 4 5 6 7 8 9 ~ 16 17 18 19, 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ~ 41 42 43 44
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
NAME
SCK DGND ENB DGND MCLK VDD5 AVDD AGND N.C AGND AVDD Reserved DGND DATA7 DATA6 DATA5 DATA4 DGND DATA3 DATA2 DATA1 DATA0 DVDD DGND N.C DVDD RESET VSYNC
I/O
I I I I I I I I I I I O O O O I O O O O I I I I O
45 46 47 48
HSYNC /DVALID DGND SDA DGND
O I I/O I
DESCRIPTION I2C Clock ; I2C clock control from I2C master Digital Ground Sensor Enable Signal ; 'H' enable normal operation 'L' disable sensor Digital Ground Master Clock (up to 15MHz) ; Global master clock for image sensor internal timing control I/O bias voltage for 5V tolerant *1) Analog Supply Voltage 3.3V Analog Ground No Connection Analog Ground Analog Supply Voltage 3.3V Reserved Digital Ground Image Data bit 7 Image Data bit 6 Image Data bit 5 Image Data bit 4 Digital Ground Image Data bit 3 Image Data bit 2 Image Data bit 1 Image Data bit 0 Digital Supply Voltage 3.3V Digital Ground No Connection Digital Supply Voltage 3.3V Hardware Reset Signal, Active Low Vertical synchronization signal / Frame start output ; Signal pulse at start of image data frame with programmable blanking duration Horizontal synchronization signal / Data valid output ; Data valid when 'H' with programmable blanking duration Digital Ground I2C Data ; I2C standard data I/O port Digital Ground
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -81999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division Register map
Register Name Mode A Mode B Mode C Row Start Address High Row Start Address Low Column Start Address High Column Start Address Low Window Height Address High Window Height Address Low Window Width Address High Window Width Address Low HSYNC Blanking Time High HSYNC Blanking Time Low VSYNC Blanking Time High VSYNC Blanking Time Low Integration Time High Integration Time Middle Integration Time Low Master Clock Divider Reset Level Control Red Color Gain Green Color Gain Blue Color Gain Pixel Bias Voltage Red Offset Gain Control Green Offset Gain Control Blue Offset Gain Control Low Reference Number High Low Reference Number Low High Reference Number High High Reference Number Low address 00h 01h 02h 10h 11h 12h 13h 14h 15h 16h 17h 20h 21h 22h 23h 25h 26h 27h 28h 30h 31h 32h 33h 34h 50h 51h 52h 57h 58h 59h 5Ah reserved reserved reserved reserved reserved reserved reserved reserved 7 6 5 4 3 2 rev_num hs_out sw_enb reserved r_ad[7:0] reserved c_ad[7:0] reserved h_ad[7:0] reserved w_ad[7:0] h_blank[15:8] h_blank[7:0] v_blank[15:8] v_blank[7:0] int_time[23:16] int_time[15:8] int_time[7:0] clk_div[3:0] rst_level[5:0] red_color[5:0] green_color[5:0] blue_color[5:0] pixel_bias[3:0] red_offset[6:0] green_offset[6:0] blue_offset[6:0] low_ref_no[15:8] low_ref_no[7:0] high_ref_no[15:8] high_ref_no[7:0] w_ad[8] h_ad[8] c_ad[8] scr_size pwr_dn shot color int_sel reserved r_ad[8] 1 0
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
model_name oper_mode reserved data_type
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 -91999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
Register Set Descriptions
All register access can though the I2C multi-byte read and write.
(1) Mode A Register (Address 00h, RO) This register consist of a model name and revision number. The upper 4 bits is model_name [3:0] and the lower 4 bits is rev_num[3:0]. For example it' s value 12h, this mean 400*300 resolution and revision2.0 chip. < model_name > 400*300 : 0001b < rev_num > Rev. 2.0 : 0010b
(2) Mode B Register (Address 01h, default : 04h, R/W) This register defines major operation mode of the chip.
n
Mode B[7:6] : oper_mode(operating mode) Define operating modes between normal operation and optical and function test operation. Test operation mode is used for optical and function test. Except for default value, these bits are reserved for manufacturer.
Bit 00 01 10 11
operating mode Normal operation Reserved Reserved Reserved
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 10 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
n
Mode B [5:4] : data_type(data types) These bits define output pixel data types. For Correlated Double Sampling(CDS), every the pixel of image sensor are measured twice, reference and data respectively, and reference values or data values can be read out through pixel data pins selectively using these control bits. To remove the noise caused by circuit, i.e. Fixed Pattern Noise, the image sensor performs the CDS in default value. Three output data types are supported as follows.
Bit 00 01 10 11
Output data type Data level - Reference level Reference level Data level Reserved
n
Mode B[3] : hs_out(HSYNC output configuration) This bit offers two types output style about HSYNC signal. HSYNC only mode and HSYNC & internal clock mode. If the hs_out is set to one, HSYNC output signal is ANDed signal of internal pixel clock and data valid. Otherwise HSYNC output pin keep data high state during valid output period. When HSYNC & internal clock mode is set, HSYNC output can be used as a pixel data output clock.
data valid MUX pixel clock Mode B[3] HSYNC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 11 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
n
Mode B[2]
: scr_size(screen size select)
Flexible screen size is very useful for customer. If the scr_size is set to high, i.e. window mode, only pixels in windowed area defined by register 10h ~ 17h can be read . But scr_size is set to low state, i.e. full screen mode, all pixels in the sensor are read out regardless the values of register 10h ~ 17h. We can select window mode or full screen mode with this bit. Full screen size is only for chip test. - window start point : x : row start address (register 10h, 11h) y : column start address (register 12h, 13h) - window end point : x : row start address + window width address (register 14h, 15h) - 1 y : column start address + window height address (register 16h, 17h) -1
n
Mode B [1] : shot(shot mode) User can select continuous frame mode or snapshot mode according to application. At the continuous frame mode, pixel data output is updated every VSYNC period. In order to set snapshot mode, it this bit to ` 1' . In that case, just single frame of pixel data will be read out, then the sensor stops operation. Snapshot mode can be used for the digital still camera applications.
n
Mode B[0] : int_sel(integration time unit select) This bit defines integration time unit i.e. line base or pixel clock base. Default mode is line unit integration but at the bright condition or if you need precise exposure time control, pixel mode is recommended. This bit related to integration time register 25h, 26h, and 27h.
Actual integration time can be calculated using three integration time registers and pixel clock period. In pixel mode, integration time = (25h, 26h, 27h) * number of pixel period. In line mode, integration time = (26h, 27h) * number of pixel per line * pixel period. (cf) number of pixel per line = 414 + HSYNC duration value
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 12 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
(3) Mode C Register (Address 02h, default : 08h, R/W)
This register controls power down and color select.
n
Mode C[3] :
sw_enb (software enable : active low)
(400*300 CMOS image sensor only)
This bit is only exist in 400*300 CMOS image sensor chip to enable image sensor operation by software. This bit has same function as ENB pin control. It' s very useful for the applications that is needed want to reduce interface pin count to CMOS image sensor. In that case, cannot ENB pin to VDD line and control the sensor using this bit. n Mode C[2] : pwr_dn(A/D converter power down)
This bit controls power down of A/D converter when sleep mode(idle state) is set by ENB pin is low or sw_enb(Mode C[3]) is high. When set to high, A/D converter is turned on whenever ENB is low or sw_enb is high. When set to low, A/D converter is turned off always regardless ENB pin state or sw_enb state . But digital block goes to power down mode always when ENB is low regardless this bit.
n
Mode C[1] :
color(color select)
This bit selects color mode or monochrome mode. Default value means color image sensor and all three ADCs are used for Bayer RGB color pattern respectively, then RGB gains are controlled independently. But when set this to one, i.e. monochrome mode, just single ADC is used for all pixels regardless RGB color. At the monochrome mode all pixels are controlled by ` G' gain only. ` R' and ` B' gain are not used. In case of monochrome image sensor, this bit should be set to ` 1' get the good image and to simplify the sensor control. (4) Row start address Register (Higher byte : Address 10h, default : 00h, R/W) (Lower byte : Address 11h, default : 06h, R/W) Define window start position row start address of display window. Should be programmed with value between 6 and 306.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 13 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
(5) Column start address Register (Higher byte : Address 12h, default : 00h, R/W) (Lower byte : Address 13h, default : 06h, R/W) Define window start position column address of display window. Should be programmed with value between 6 and 406.
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
(6) Window Height address Register (Higher byte : Address 14h, default : 01h, R/W) (Lower byte : Address 15h, default : 2Eh, R/W) Define display window height. If you need smaller display window height, decrease the value. Window end position row address = row start address + window height address -1
(7) Window width address Register (Higher byte : Address 16h, default : 01h, R/W) (Lower byte : Address 17h, default : 92h, R/W) Define display window width. If you need smaller display window width, decrease the value. Window end position column address = column start address + window width address -1 Note : Display window programming. < Display Window Programming > The 400*300 resolution chip can read any user specific window area within active window area. This is called panning function. For this function, ` row start' , ` column start' , ` width' , and ` height' can be programmed with four sets of register pair.
n n n n
FRS : FCS : FWH : FWW :
Frame Row Start Frame Column Start Frame window Height Frame Window Width
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 14 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
Panning window can be programmed as below.
(413,313) (0,313)
(407,307)
manufacturer area active window area
{FRSU, FRSL} {FWWU, FWWL} {FCSU, FCSL} (6,6)
(413,0)
(0,0)
Note 1) Accessible pixel array size is 402*302. The edge of accessible pixel array may be commonly dedicated for just color interpolation. In the case of a color image sensor the interpolation is needed to get all R,G,B color value for each pixel from a Bayer color image. So one more extra pixel line is needed at the edge of pixel array that you want to be displayed. That is, to make 400*300 effective window, 402*302 pixel array necessary. You have to consider this interpolation line when you program the ` Frame register' . For example, if you want to get 300*250 image size, you have to program 302*252 to frame register.
FRSU, FRSL FCSU, FCSL
6 6
FWHU, FWHL FWWU, FWWL
302 402
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 15 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
< Pixel Array Structure >
total pixel : 416 * 316 +1 : dummy area +1 : dummy zone for set of color pattern +2 : optical block zone +3 : margin for metal 3 slope +1 : interpolation area
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
pixel array : 400 * 300
---- R G GBG B RG
----
BG GR
active window area (402 * 302) accessible address range(414 * 314)
(8) HSYNC Blanking Time Register (Higher byte : Address 20h, default : 00h, R/W) (Lower byte : Address 21h, default : 03h, R/W) The HSYNC blanking time defines HSYNC low duration between data valid HSYNC high, pixel unit . HSYNC low duration is HSYNC blanking time plus twelve in pixel unit for example, default HSYNC low duration is 15 pixels because register value is 3. It' s used to change duration between current line end and next line start.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 16 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
(9) VSYNC Blanking Time Register (Higher byte : Address 22h, default : 00h, R/W) (Lower byte : Address 23h, default : 03h, R/W) The VSYNC blank, and time defines VSYNC active duration in pixel unit . HSYNC blanking, VSYNC blank are used to fit the CMOS sensor display timing to external timing requirements. (10) Integration time Register (High (Low byte : Address 25h, default : 00h, R/W) byte : Address 27h, default : f4h, R/W)
(Middle byte : Address 26h, default : 01h, R/W)
Each pixel has a photo diode in which the incoming photons are converted to electrons. Integration time mean exposure time so these registers defines exposure time. According to settings int_sel of Mode B register, the integration time is controlled with line or pixel unit. Small value means short exposure time and large value means long exposure time for bright condition. The value should be large for dark condition. Default value setting 500 lines, this value is useful for normal office condition. If you stay in outdoor condition, this value should be decreased. But under dark condition, this value should be increased to get a good image quality. Increasing value may decrease frame rate. Finally, integration time is very important for frame rate and image quality. For line mode exposure, register 26h and 27h are used. For pixel mode exposure, all three register 25h ~ 27h are used. To control exposure time precisely, the pixel mode should be used. This register may be used for Auto Exposure control.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 17 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
(11) Operating Clock Divider (Address 28h, default:00h, R/W) This register generates divided digital clock depending on the settings clk_div [3:0], digital block can divide MCLK down by 1 through 2048 as shown in Table 1. clk_div[3:0] 0000 0001 0010 0011 0100 0101 units no division MCLK/2 MCLK/4 MCLK/8 MCLK/16 MCLK/32 clk_div[3:0] 0101 0111 1000 1001 1010 1011 units MCLK/64 MCLK/128 MCLK/256 MCLK/512 MCLK/1024 MCLK/2048
Table 1. Operating Clock Control Register (12) Reset Level Control Register (Address 30h, default:38h, R/W) This register controls reference voltage level for start point of data reading. If the register value is too large or too small, the vertical Fixed Pattern Noise(FPN) can be occurred. To Get rid of FPN, this register must have a suitable value. Optimum reset revel can be found using Low reference number registers 57h ~ 58h and High reference number registers 59h ~ 5ah. If there is some large value in Low reference number registers, the value of Reset Level control register should be increased. If there is some large value in High reference number registers, the value of register should be decrease. Optimum reset revel is achieved when value of Low reference level number registers and value of High reference number registers is minimized. (13) Color Gain Register Red Color Gain Register : (Address 31h, default:1Eh, R/W)
Green Color Gain Register : (Address 32h, default:h1Eh, R/W) Blue Color Gain Register : (Address 33h, default:h1Eh, R/W) These registers are used to amplify the analog pixel output. If the gain register value is decreased, the amplification is increased. Therefore under the dark light source condition, the pixel output have to be amplified by decreasing gain value to get good image. There are three Gain registers to control RGB colors independently. In the case of monochrome image sensor, use only Green Color Gain Register. Available program range is 0 ~ 63 but too small value can cause FPN. The register value have to chosen within the range that doesn' t cause FPN. Recommended range is 20 ~63. These register can be used for Auto White Balance control and Auto Exposure control.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 18 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
(14) Pixel Bias Voltage Register (Address 34h, default:02h, R/W) This register controls pixel reference level by controlling bias current of pixel output sensing load transistor. It controls pixel output level itself, compare with that revel register adjust A/D Converter circuit to calibrate reference level for data reading. Available program range is 0 ~ 7. The larger register value causes the higher bias current and low pixel output reference level. This register is option for manufacturer. Users may use default setting and don' t changed value. (15) Low Reference Number Register(low_ref_no) High : (Address 57h default:00h, Read Only) Low : (Address 58h, default:00h, Read Only) Low Reference Number Registers indicates number of pixels in frame that have a value less then 5. A reference level values of each pixel is compare with ` 5' , and accumulated to these registers during read state. This counter value called low_ref_no, consist of two bytes and it is read only registers. Real number of pixels that have value less than 5 is the twice of these register value. If low_ref_no is big value, you must increase data value of Reset Level Control Register. These registers are updated after every VSYNC signal. (16) High Reference Number Register (high_ref_no) High : (Address 59h, default:00h, Read Only) Low : (Address 5Ah, default:00h, Read Only) High Reference Number Registers indicates number of pixels in a frame that have a value great then 123. Reference level values of each pixels is compared with ` 123' , and accumulated to these registers during read state. This counter value called high_ref_no, consist of two bytes and it is read only registers. Real number of pixels that have value great than 123 is the twice of these register value. If high_ref_no is big value, you must decrease data value of Reset Level Control Register. These registers are also updated after every VSYNC signal.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 19 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division FRAME TIMING DIAGRAMS
There are two frame timing cases, l l Integration Time < EffectiveWindowHeight * Scale Integration Time > EffectiveWindowHeight * Scale
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
EffectiveWindowHeight is equal to the number of data lines generated in a frame and is defined to be selected by if((RowStartAddress + WindowHeight + 1) <= (SensorArrayHeight) EffectiveWindowHeight = WindowHeight; else EffectiveWidnowHeight = (SensorArrayHeight - RowStartAddress - 1); For example, RowStartAddress = 200 and WindowHeight = 300, EffectiveWindowHeight is 113 and 113 data lines per a frame are generated. Note : The above selection logic is somewhat confusing in respect of general counting measure. It' s partly due to the mixed use of indexing start points, i.e. ` 0' and ` 1' in the design. Therefore in order to avoid the confusion it is desirable to just follows the equation when you estimate the frame rate.
SensorArrayWidth [414] (0,0) SensorArrayHeight [314] EffectiveWindowHeight [113] RowStartAddress [200] WindowHeight [300]
Scale is selected according to Integration Time Mode by If(PixelMode) else Scale = SensorArrayWidth; // For400*300 resolution chip, SensorArrayWidth is 414 Scale = 1;
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 20 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow immediately after current frame' s last line has been produced. Instead, one of the following two idle time slots is inserted according to Integration Time Mode before next frame VSYNC gets active.
< Idle Slots >
l l
Line Mode: (Integration Time - EffectiveWindowHeight) * 1024 clocks Pixel Mode: (Integration Time - EffectiveWindowHeigth * Scale) = (Integration Time - EffectiveWindowHeigth * SensorArrayWidth) clocks
Each Frame Timing of the above cases may be decomposed into four timing segments
l l l l
Initial Data Setup Time after ENB gets active Even Line Odd Line Frame Transition
The subsections will describe frame timing diagram for said frame time cases, (Integration Time < Effective Window Height * Scale) and (Integration Time > Effective Window Height * Scale)
(1) Frame Timing Diagram for Integration Time < (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress
= 6;
WindowHeight = 302; WindowWidth = 402;
ColumnStartAddress = 6;
IntegrationTime = 200 [Line Mode];
EffectiveWindowHeight is "302" for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 > (6 + 302 + 1), is met, and Scale is "1" for integration time is line mode.
Therefore, (Integration Time< EffectiveWindowHeight * Scale), i.e. 200 < 302 * 1, is met.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 21 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
Overall Frames Sequence Frame 0 Frame 1 Frame 2
MCLK
ENB
VSYNC
Delay Slots
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 22 1999 Hyundai System IC Division
Initial Data Setup Time
Line 300
Line 301
Line 300
Line 301
Line 300
Line 301
VSYNC
VSYNC
VSYNC
Line 0
Line 1
Line 2
Line 0
Line 1
Line 2
Line 0
Line 1
Line 2 ....
ENB+ Deglitch 2 clocks
....
....
....
Sensor Reset SensorArrayHeight clocks [314 clocks]
Integration Time * Scale clocks [200 * 414 clocks]
One Line Time Delay (SensorArrayWidth + HBLANK) clocks [417 clocks]
VSYNC 3 clocks
Fig. 1 Initial Data Setup Time after ENB gets active
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
MCLK
HSYNC B DATA
Line Head Blank 12 clocks
G
B
G
B
G
B
G
Time Slot
IMAGE RAW DATA Window Width 804 clocks
Line Tail Blank 12 clocks
HBLANK 3 clocks
Clock Ruler
SensorArrayWidth (828) HBLANK(3)
Fig.2 Even Line Data Timing
MCLK
HSYNC G DATA
Line Head Blank 12 clocks
R
G
R
G
R
G
R
Time Slot
IMAGE RAW DATA Window Width 804 clocks
Line Tail Blank 12 clocks
HBLANK 3 clocks
Clock Ruler
SensorArrayWidth (828) HBLANK(3)
Fig.3 Odd Line Data Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 23 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
MCLK
HSYNC
VSYNC
DATA
.....
G
R
B
G
B
.......
Time Slot
IMAGE RAW DATA Window Width 804 clocks
Line Tail Blank 12 clocks
HBLANK 3 clocks
VSYNC 3 clocks
Line Head Blank 12 clocks
IMAGE RAW DATA Window Width 804 clocks
Integration Time < EffectiveWindowHeight * Scale Fig.4 Frame Transition Timing
(2) Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows RowStartAddress = 6; WindowHeight = 302; WindowWidth = 402; ColumnStartAddress = 6;
IntegrationTime = 600 [Line Mode]; EffectiveWindowHeight is "302" for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 > (6 + 302 + 1), is met, and Scale is "1" for integration time is line mode. Therefore, (Integration Time < EffectiveWindowHeight * Scale), i.e. 600 > 302 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 302) * 1024 clocks idle slot, is inserted before the next frame initiation.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 24 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
Overall Frames Sequence
Frame 0 Frame 1 Frame 2
MCLK
ENB
VSYNC
Delay Slots
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 25 1999 Hyundai System IC Division
Initial Data Setup Time
Idle Time
Idle Time
Idle Time
Line 300
Line 301
Line 300
Line 301
Line 300
Line 301
VSYNC
VSYNC
VSYNC
Line 0
Line 1
Line 2
Line 0
Line 1
Line 2
Line 0
Line 1
Line 2 ....
....
....
ENB Deglitch 2 clocks
Sensor Reset SensorArrayHeight clocks [314 clocks]
Integration Time * Scale clocks [600 * 414 clocks]
One Line Time Delay (SensorArrayWidth + HBLANK) clocks [417 clocks]
VSYNC 3 clocks
Fig. 5 Initial Data Setup Time after ENB gets active
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
MCLK
HSYNC B DATA
Line Head Blank 12 clocks
G
B
G
B
G
B
G
Time Slot
IMAGE RAW DATA Window Width 804 clocks
Line Tail Blank 12 clocks
HBLANK 3 clocks
Clock Ruler
SensorArrayWidth (828) HBLANK(3)
Fig.6 Even Line Data Timing
MCLK
HSYNC G DATA
Line Head Blank 12 clocks
R
G
R
G
R
G
R
Time Slot
IMAGE RAW DATA Window Width 804 clocks
Line Tail Blank 12 clocks
HBLANK 3 clocks
Clock Ruler
SensorArrayWidth (828) HBLANK(3)
Fig.7 Odd Line Data Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 26 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
MCLK
HSYNC
VSYNC
.... DATA
G
R
B
G
.....
Time Slot
IMAGE RAW DATA Window Width 804 clocks
Line Tail Blank 12 clocks
HBLANK 3 clocks
Idle Slot (Integration Time EffectiveWindowHei ght) * 1024 = (600 - 482) * 1024
VSYNC 3 clocks
Line Head Blank 12 clocks
IMAGE RAW DATA Window Width 804 clocks
Integration Time > EffectiveWindowHeight * Scale Fig.8 Frame Transition Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 27 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
PACKAGE DIMENSION (48 PIN CLCC)
UNIT: mm
C
0.53 0.98
* C : Center of Image Area
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 28 1999 Hyundai System IC Division
HB7121B
Electronics Industries Co., Ltd. System IC Division MEMO
PRELIMINARY
CMOS IMAGE SENSOR With 8-bit ADC
Hyundai Electronics Industries Co., Ltd System IC Division
Headquarter & Factory
San 136-1,Ami-Ri,Bubal-Eub,Ichon-Si,Kyoungki-Do,Korea 467-860 Tel : 82-336-630-2042/2484, Fax : 82-336-639-1412, E-mail : wkkim@hei.co.kr
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. NO patent licenses are implied. DA21991011R_1.0 - 29 1999 Hyundai System IC Division

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